1. Field of the Invention
The present invention relates to a decoder circuit for a semiconductor memory device such as a dynamic random access memory (DRAM).
2. Description of the Prior Art
In a DRAM of 1 MB, the access time thereof is typically 100 ns. As the volume of DRAM is increased a shorter access time is demanded. In fact, the access time of 4 MB DRAM is typically 80 ns and that of 16 MB DRAM is typically required to speed-up to 60 ns. Further, it is forecasted that 64 MB DRAM will have an access time of 40 to 50 ns.
In an improved 64 MB DRAM, the time for reading data from and/or writing data into a memory cell is speeded up from 14.5 ns to 9.5 ns with respect to column switches. Further, the time for data output measured after the operations of the column switch is also speeded up from 14.5 ns to 10.5 ns. However, the time needed from an input of RAS signal the rising edge of a word line still needs 13 ns. In order to speed up the access time more, it is necessary to quicken the word line selecting operations. This necessitates a decoder circuit having a much faster operation time.
Conventionally, some improvements related to the memory cell and the sense amplifier of DRAM have been proposed in order to speed up the same using differential amplifiers for the sense amplifiers (See, for example, Japanese patent laid-open publications No. S 55-34394, S 55-3089, S 55-3496 and so on).
Further, in Japanese laid-open publications No. H 3-34192, there has been proposed to speed up the differential amplifier to be used for the sense amplifier which reads data from and writes data into the memory cell .
However, as far as the decoder circuit as a peripheral circuit of DRAM is concerned, nothing has been proposed to speed up the access time of DRAM.
FIG. 19 shows a conventional decoder circuit of NOR type. In operational of this circuit, when a P-channel transistor 204 is turned on at "L" level of a clock signal .PHI.s, a decode output line 201 is precharged up to a power source level at first. If input signal decode lines AO and AN, namely, 212 and 221 are selected, input signal decoding signals of "L" level are applied thereto and thereby, N channel transistors 231 and 232 are turned off. Thus, the decode output line 201 is not discharged and a signal of "H" level is outputted as a decode signal through drivers 202 and 203 functioning as buffers.
If 212 and 221 are not selected, an input signal decoding signal of "H" level is applied to either or both of them, and thereby, at least one of N-channel transistors 231 and 232 is turned on. Thus, the decode output line 201 is discharged down to "L" level and, thereby, a signal of "L" level is outputted through drivers 202 and 203.
This type of decoder circuit has a disadvantage in that it is difficult to speed up because the decoder circuit does not operate until the decode line has been discharged perfectly. Further, it has a disadvantage in that a large circuit occupation area is needed because the area of each transistor for pull-down is inevitably enlarged to give a high driving capability.
In a semiconductor memory of a large volume, some problems are caused as follows; delay time to an input signal becomes serious since the wiring length thereof is needed to be lengthy, the access time becomes long because the number of memories connected to each word line is increased resulting in a large wiring capacitance thereof, and an area to be shared for the address decode circuit becomes large because the bit number of an input signal is increased.